1. Field of the Invention
The present invention relates to a semiconductor device and a fabricating method thereof, and more particularly to a semiconductor device and a method of fabricating the device to prevent a gate oxide layer from being deteriorated by damage induced during a plasma fabrication process.
2. Description of the Prior Art
High integration of the semiconductor device has been achieved, in general, through advancements in photo processes and etching processes such as the plasma etching process or the reactivity ion etching process. During such etching processes, electric charge can be accumulated at the floating gate oxide layer, thereby causing a defect on the gate oxide layer and further deteriorating operational properties of the semiconductor device.
Recent trends have led to the common use of a double-metal layering process for fabricating high-speed semiconductor devices. As device integration increases in this manner, the high-density plasma etching process becomes increasingly important for etching narrow lines. During the plasma etching process, serious damage may be inflicted on the gate oxide layer, causing variations in threshold voltage or deterioration of the drain saturated current (Idsat). As a result, the expected lifetime of the gate oxide layer becomes shorter, and operational failure of the semiconductor device is more likely.
In an attempt to alleviate this problem, others have designed a semiconductor device configuration for mitigating deterioration of the gate oxide layer arising from the plasma process, as shown in FIG. 1. In this configuration, the active region of the P type silicon substrate 10 is constructed with N+ diffusion regions 11, 13 to provide transistor sources and drains, and an N+ diffusion region 15 to serve as a cathode for a device protection diode. A polysilicon layer 30 for a gate electrode is formed on the gate oxide layer 20 between the N+ diffusion regions 11, 13. Metal layers 51, 53 are electrically connected to the N+ diffusion regions 11, 13 respectively through contact holes of an inter-level insulating layer 40, and a metal pathway 55 is electrically connected between the N+ diffusion region 15 and the gate electrode 30 through a contact hole in the inter-level insulating layer 40. The P-type silicon substrate 10 below the N+ diffusion region 15 operates as an anode of the protection diode.
In the embodiment of FIG. 1, deterioration of the gate oxide layer 20 due to damage induced in the plasma etching process necessary for deposition of the metal layer 50 is mitigated because the polysilicon layer 30 for the gate electrode and N+ diffusion region 15 for the cathode of the protection diode are electrically connected by the metal layer 55.
However, electric charge in the form of ions, radicals or electrons is accumulated on the polysilicon layer 30 during the selective etching process. Consequently, the charged ions, radicals or electrons flow, via Fowler-Nordheim tunneling current or direct-tunneling current, through the gate oxide layer 20 to the silicon substrate 10. In this manner, the gate oxide layer 20 can suffer from deterioration due to the damage inflicted during the plasma etching process.